The invention relates to semiconductor devices. More particularly the invention relates to improvements in the switchable routing networks used in many semiconductor devices to route signals across the device.
Throughout the specification, P and N-channel MOS (metal oxide semiconductor) devices (PMOS and NMOS) are described in terms of their respective gate, drain and source nodes to help clarify the structure and operation of the alternative embodiments. PMOS devices transmit positive current when the signal on the gate is low, and cease transmitting current when the signal on the gate is high. NMOS devices transmit positive current when the signal on the gate is high, and cease transmitting positive current when the signal on the gate is low.
According to standard convention, positive current flows from the drain to the source node in NMOS devices, and flows from the source to the drain in PMOS devices. The source and drain node conventions are used only to help describe the structure and operation of embodiments of the invention and are not intended to limit the scope of the invention. It is possible to operate MOS transistors in reverse, especially if the source and drain regions are symmetrical. As such, the relative positions of the drain and source are not critical to the disclosed embodiments of the invention.
Turning to FIG. 12, many semiconductor devices are composed of a number of processing elements 10 connected via a configurable routing network 20. For example, reconfigurable devices, such as field programmable gate arrays (“FPGAs”), processor arrays and reconfigurable arithmetic arrays (“RAAs”), normally include a number of processing elements connected together by a general-purpose interconnect network capable of making links between various combinations of processing elements. Similarly, integrated devices include several processors, peripherals and memories connected via one or more shared busses. FIG. 12 depicts a portion of such a semiconductor device. The semiconductor device of FIG. 12 includes additional processing elements, which are omitted from FIG. 12 in order to clearly show the details of the circuit. It is sometimes useful to provide input buffer circuits 80 between the configurable routing network 20 and the processing elements 10. These input buffer circuits 80 can be buffers that simply propagate an input value, or simple logic devices such as CMOS inverters, NAND gates, or NOR gates, or can be more complex circuits adapted to perform various functions as desired by the designer of the semiconductor device.
The configurable routing network 20 carries signals from one processing element 10 to another. The signals proceed from the processing device outputs 12 of the various processing elements 10 across the configurable routine network 20 to the processing device inputs 15 of the various processing elements 10. For CMOS circuits these signals are typically a series of binary values, expressed as either a high voltage corresponding to a logic “1” and normally equal to Vdd, the positive supply voltage 60, or a low voltage, corresponding to a logic “0” and normally equal to Gnd, the ground supply voltage 70.
The routing network 20 typically comprises a set of wire segments 30 and a set of active devices, configured as switches 40, that can make or break connections between the wire segments 30. By selectively making and breaking connections between wire segments 30, the routing network 20 is capable of making a variety of connections between the various processing elements 10 on the device. The switches 40 at the top and bottom of FIG. 12 provide connections to the additional processing elements which are not shown in FIG. 12. These connections can be dynamically varied as the requirements of the processing elements 10 change. The switches 40 are controlled by signals on the control wires 50, typically by the state of the device they are part of, or sometimes by the state of another device.
There are various types of switches 40 that can be used in switchable routing networks. One type of switch 40 that is useful in designing routing networks is a single transistor, known as a pass transistor, with its source and drain connected to a pair of the wire segments 30 in the routing network. Pass transistors are a good choice because they do not take up much space on the semiconductor device, they can propagate signals across the wire segments 30 in either direction, and they do not consume very much power, because there are no active circuits in the routing path. Power is only used to charge and discharge the wire segments 30.
However, implementing the switches 40 as pass transistors also suffers from a disadvantage. Depending on the type of pass transistor used, either the highest voltage that can propagate through the pass transistor is less than the gate voltage (normally Vdd to turn on an NMOS transistor), or the lowest voltage that can propagate through the pass transistor is greater than the gate voltage (normally Gnd to turn on a PMOS transistor). For an NMOS pass transistor, the reduced high signal is lower than the gate voltage by an amount equal to the threshold voltage Vt of the transistor, yielding a reduced high signal Vdd−Vt. For a PMOS pass transistor, the increased low signal is greater than the gate voltage by an amount equal to the absolute value of the threshold voltage Vt of the transistor, yielding an increased low signal of Gnd−Vt. (PMOS transistors by convention have negative threshold voltages, so Gnd−Vt is greater than Gnd.) Therefore an undegraded signal varying between Vdd and Gnd will be degraded as it propagates through a pass transistor. Other active devices may similarly alter either the high or low signals, depending on the active device. Because of this voltage alteration effect of the pass transistors, logic devices such as the input buffer circuits 80 which receive the signals sent through the pass transistors receive signals that may not be high enough or low enough to guarantee to turn the transistors within the logic devices on or off.
For example, if a reduced high signal from an NMOS pass transistor is provided to the gate of a PMOS transistor, in an input buffer circuit 80, that has the positive supply voltage Vdd provided on the source, then the reduced high signal will be insufficient to turn the PMOS transistor fully off, and some current will leak through the PMOS transistor. Similarly, if an increased low signal is provided to the gate of an NMOS transistor, in an input buffer circuit 80, that has the ground voltage Gnd provided on the source, then the increased low signal will be insufficient to turn the NMOS transistor fully off, and some current will leak through the NMOS transistor. This phenomenon is not unique to pass transistor switches in routing networks. Similar issues arise anytime a high signal is reduced or a low signal is increased as it is propagated across any active or powered device (e.g. transistors, rectifiers, amplifiers, etc.).
Various means have been used to attempt to resolve the voltage alteration problem caused by active devices such as the pass transistors in a routing network. For example, the reduced high signal on the output of the pass transistor can be raised to a level high enough to ensure that other devices attached to the output of the pass transistor can be turned on or off, by reducing the threshold voltage Vt of the pass transistor.
In order to reduce Vt, a more complex process of creating the silicon substrate is required. It is possible to design devices with a lower Vt, but an extra processing stage is required. Additionally, this extra step typically means that the lower Vt elements have to be physically spaced further from the normal Vt elements, which consumes valuable space on the silicon. Also, a lower Vt means that there is a stronger leakage current when the transistor is switched off, which wastes power.
Another solution to the voltage alteration problem is to use a level-restoring circuit to pull the reduced high signal back up to the high signal, or pull the increased low signal back down to the low signal. There are two popular types of circuits for restoring voltages. First a circuit known as a “weak pull-up” circuit can be used to pull up a reduced high signal (similarly a weak pull-down can pull down an increased low signal.) Second, a differential amplifier circuit can be used to push both reduced high and increased low signals to the respective high or low values.
The circuit of FIG. 1 is an example of a weak pull-up circuit. The circuit of FIG. 1 is shown using an inverter 140 as the logic device to which the reduced high signal is provided. The weak pull-up circuit functions similarly for other devices such as NAND gates. Weak pull-up circuits, however, are not useful for devices such as NOR gates. In order for a weak pull-up to be useful, the output of the gate must be low if and only if the input to which the pull-up is attached is high. This condition is met for inverters and NAND gates, but not NOR gates—the NOR output could be low if the other input was high.
The inverter 140 requires a high signal equal to Vdd in order to be certain of being fully activated. A reduced high signal is received on the input 110. This reduced high signal is propagated to the inverter 140, which causes the inverter 140 to emit the inverse of this reduced high signal, an increased low signal somewhere above the low signal (the low signal being equal to Gnd). This increased low signal is passed to the gate of the PMOS transistor 130, which causes the PMOS transistor 130 to turn on. The PMOS transistor 130 is then able to pull the input 110 up to the full Vdd level present on the positive voltage supply input 120. Thus, the reduced high signal on the input 110 is pulled up to the full Vdd level and the inverter 140 is fully activated, propagating the full low voltage Gnd to the output 150. Alternatively, an increased low signal on the input 110 can be pulled down to a full low voltage Gnd by replacing the PMOS transistor 130 with an NMOS transistor, and replacing the Vdd voltage on the positive voltage supply input 120 with a Gnd voltage.
This circuit has a significant drawback, however. Selecting the proper strength of the transistor 130 is important for efficient operation of the circuit, yet non-trivial. Transistor strength is a measurement of the resistance of the transistor when it is conducting current. Strong transistors conduct a greater current than weak transistors. If the transistor 130 is too weak, then it takes a long time for the transistor 130 to pull the input all the way up (or down for NMOS pull down transistors), during which time the inverter 140 is dissipating power. If the transistor 130 is too strong, then it takes time for the driving circuit to pull against the transistor when trying to drive a low onto the input 110 in order to flip the inverter, or for an NMOS pull down transistor when trying to drive a high onto the input 110. The need to pull against the resistive load from the transistor 130 also increases power dissipation.
Selecting the proper strength for the transistor is especially difficult in reconfigurable arrays, since the optimal strength is dependent on the resistance of the path through the array from the original source of the signal to the device targeted by the signal. Since the array is reconfigurable, this path is variable in length depending on the application configured onto the array, and thus the resistance is variable, not constant. Therefore the only way to select a safe value for the pull-up transistor is to use a value that is safe for the worst case path—i.e. a value that is guaranteed to be sub-optimal for the vast majority of paths. The safe value is a value that is weak enough that its resistance can always be overcome by any path through the array.
Another solution is the differential amplifier circuit shown in FIG. 2. In this circuit, the input signal on the input 210 is compared with a reference signal Vref on the reference input 280. Vref is selected to be halfway between the high signal and the low signal that propagate through the routing network. The positive voltage supply input 220 supplies the positive supply voltage Vdd to the two PMOS transistors 230, 240. The ground voltage supply input 270 supplies the ground supply voltage Gnd to the two NMOS transistors 250, 260. The drains of the two PMOS transistors 230, 240 connect to the ground 270, via the two NMOS transistors 250, 260. The drains of each of the two PMOS transistors 230, 240 also connect to the gate of the other PMOS transistor. The first NMOS transistor 250 is controlled by the input signal on the input 210. The second NMOS transistor 260 is controlled by the Vref signal on the reference input 280. Finally, the output 290 is connected to the drain of the second PMOS transistor 240.
The differential amplifier is constructed such that the two PMOS transistors 230, 240 will not both normally be on simultaneously. If one of the two PMOS transistors 230, 240 has a low drain voltage it will turn the other on, and thereby cause the other's drain voltage (and its own gate voltage) to be high, turning itself off and ensuring that its own drain voltage remains low. The drain voltages are controlled by the NMOS transistors 250, 260 trying to pull down the voltage to Gnd. Whichever of the two NMOS transistors 250, 260 has a higher signal on its gate will pull down more strongly, forcing a lower voltage onto the drain of the corresponding PMOS transistor 230, 240 and consequently turning on the other PMOS transistor. Therefore, if the signal on the input 210 is less than the Vref signal on the reference input 280, then the first PMOS transistor 230 is turned on, the second PMOS transistor 240 is turned off, and the output 290 goes down to Gnd. If the signal on the input 210 is greater than the Vref signal on the voltage input 280, then the second PMOS transistor 240 is turned on, the first PMOS transistor 230 is turned off, and the output 290 goes up to Vdd. Thus, since Vref is selected to be halfway between the high and low input signal levels, any input signal which is closer to a high than a low results in an output equal to Vdd, and any input signal that is closer to a low than a high results in an output equal to Gnd.
This circuit, however, wastes power, because of the resistive paths from Vdd to Gnd across the transistors 230, 240, 250, 260. Since the second NMOS transistor 260 is always partially conducting, there is a constant power drain through the amplifier whenever the output 290 is high. The extra power consumption of the differential amplifier circuit compromises the power benefits of using a pass transistor network in the first place.
Therefore, systems are needed to easily and optimally compensate for the effects of the routing network on the voltages propagated through the network, without increasing power dissipation in the semiconductor device, and with a small number of additional components.